Logic Synthesis for Disjunctions of Boolean Functions

This paper develops theoretical foundations and presents a practical algorithm for optimizing multi-output Boolean function M(x) whose outputs are combined using Boolean OR operator into a single-output Boolean function S(x). The proposed algorithm simplifies the logic structure of function M(x) and may change or remove some of its outputs, while preserving the functionality of function S(x). Applications of the proposed algorithm are (1) optimization of Boolean networks containing multi-input AND/OR gates, (2) minimization of sets of interpolants in interpolationbased model checking, (3) minimization of the structural representations of sets of states in circuit-based reachability analysis, to mention just a few. Experiments will be conducted to show the practicality of the proposed approach.